14. Input-Output

I/O ports are visible in address space similarly to memory locations
Ports may be mapped in memory space or a separate, distinct address space, called input-output space
In x86 - I/O space accesses only using special instructions - IN and OUT

Tri-state buffer

Electronic component (logic gate) determining the state of buffer
If enabled - buffer output equal to logic state
If disabled - buffer output turned off

Exchanging data with I/O devices

Data in memory cell may be accesses (read/written) at any time
I/O device may only be accessed when the device is ready
key code may be only read after key press
character may be sent to printed when printer has accepted previous character
Data transfer requires synchronization - watching device readiness
Synchronization with I/O devices may be achieved via:

• Polling
• Interrupts
• Direct Memory Access (DMA)

Polling

May be implemented in software without any additional hardware overhead
Takes processor time - infinite loop
Only suitable for simple single-process systems

Interrupts

Device transition to ready state generates an interrupt
Process requests an I/O transfer from OS
if device ready - transfer data and process continues
if not ready - process is suspended
Interrupt service routine causes the activation of a previously suspended process
In reality much more complex - process queues, data buffering
Marginal hardware overhead, but significantly more complex software
Other processes may execute while device is not ready
Good solutions for not too fast devices
Problem - if interrupts are too frequent, time spend on context switching and operations on task queues in the OS may saturate the processor
cannot be used for fast devices (disks, network controllers)

Direct memory access

Data transfer between device and computer's memory controlled by DMA controller without engaging the processor
DMA controller:

• Memory data buffer address register - loaded by software with starting buffer address before block transfer, incremented after every data transfer
• Data counter register - loaded with block length, decremented after every transfer
  I/O device sends transfer request to DMA controller
  DMA controller disconnects processor from bus and performs requested transfer
  Processor programs DMA controller with transfer parameters
  After completion of transfer, interrupt is signaled - one interrupt service per block

Characteristics

Requires additional hardware (with VLSI almost no cost)
Earlier implemented as separate functional block, now is incorporated into device controller
Frees processor from transmission control
Commonly used for fast devices - disks, LAN, sound, graphic controllers, USB

Mass storage devices

Programming model - registers

• starting block number register
• no. of blocks to be transferred
• command register - read/write/verify
• status register
  MSD usually use DMA

Hard Disk Drive (HDD)

Based on rotation speeds
Data transfer speed ~200MB/s

Semiconductor Mass Storage Devices (SDD)

No moving components
Very fast read, slow writing
Memory must be erased before writing
Performance limited mainly by interface characteristics:

• SATA-3 - 600MB/s
• PCIe x4 - 2-8GB/s