5. Application programming model

4 Models:

CISC - Complex Instruction Set Computer
RISC - Reduced Instruction Set Computer
The names refer to the complexity of individual instructions, not the complexity of the instruction list

RISC processors may have more individual instructions than CISC machines

CISC

Characteristics

Processor's instructions should reflect HLL instructions
Single HLL statements translated into one or few processor instructions

Registers store intermediate results and addresses, HLL-visible data is saved in memory
Instructions should operate on memory data

Instructions operate on arguments of various lengths
Operand length is encoded in the instruction

Major CISC architectures:

Rich set of addressing modes
Necessary to implement effective accesses to memory arguments
Stack operations implemented in the instruction set
max. 16 registers
Conditional operations model - usually using flags
Mostly two-arguments instructions - the result overwrites one of source arguments

Problems

RISC

Major contemporary architectures
Characteristics

Scalar local data stored in registers

Bit register set - at least 16 registers, usually 32/31
Register set should be big enough to accommodate arguments and scalar local variables

Three-arguments instructions do not destroy source arguments
Local data not overwritten while processing

Infrequent memory operations do not require sophisticated addressing modes
Simple instruction encoding

Simple instructions can be executed using simple and fast execution unit
Every instruction has only one destination argument
At most one memory reference in a single instruction

Complex operations may be synthesized using a sequence of instructions

Arithmetic and logical instructions operate only on register and immediate arguments
No operations using data stored in memory
Argument length equal to register size
No 8 or 16-bit operations

Only two kinds of instructions operate on memory data and specify argument size: Load and Store
So-called "load-store architecture"

More instructions = longer programs

All instructions have the same length

Only one or two memory addressing modes - register direct with displacement, double-register indirect

Problems

Big memory footprint of the program
Even simple instructions occupy 32 bits

Lack of operations common in HLL
Push & Pop

During call procedure, the return addr. cannot be stored on the stack - must be stored in a reg.
The register used for this purpose is called a return addr. reg. (MIPS - $ra) or a link reg. (ARM - LR)

VLIW

One word (block) containing several instructions, which can be executed instantaneously

3 or more operations contained in single, long instruction

Post-RISC

Mostly RISC with major problems removed

Usually two instruction lengths - 16 and 32 bits
Compact instructions consume less memory and can be fetched faster

Stack implemented in instruction set - Push & Pop
Also Push & Pop multiple registers in a single instruction

Examples:

Instruction representation in memory

Instructions are stored in memory similarly to data - as binary word
CISC - instructions of various lengths
RISC - fixed length of instructions (usually 32-bit)
Post-RISC - 2 instruction lengths

Instruction notation

Orthogonalities in CISC

Well-designed CISC model is characterized by:

Instruction classes

Integer - data copy (transfer, move), stack operations, arithmetic and logic operations, compare, value test, single bit operations, bit field operations, counting, masking, control transfer (jump, branch, procedure call and return), HLL support (stack frame, etc.), OS interface
Floating point - transfer, conversion, arithmetic, compare
Vector - transfer, arithmetic & logic, compare, shuffle
OS support - exception processing, resource management

ARM architecture

Very hard do program in
Started as Post-RISC
Common in embedded applications (Bluetooth, network switches, wireless access points)
Conditional operation model using flags
Conditional execution of most instructions in 32-bit ARM mode
Stack operations, including PUSH/POP multiple registers

Instruction sets

Initially 32-bit instructions
3 arguments
mostly conditional - instruction specify execution condition

Newer implementations have an alternate instruction set
Thumb (v5), Thumb2 (v6 and newer)
16 and 32-bit instructions
Limited access to some registers
Conditional instructions - branches, IT instruction
If both ARM and Thumb modes are implemented in hardware, switching is achieved via BX instruction

Cortex-M - Post-RISC version of ARM

32-bit ARM processors for microcontrollers
Thumb2 instruction set
Optimized system architecture
Super cheap microcontrollers