Computer Architecture

Lectures

University/WUT/ECOAR/0. InitLecture
University/WUT/ECOAR/1. Basics
University/WUT/ECOAR/2. Data
University/WUT/ECOAR/3. Requirements of HLL and application synthesis
University/WUT/ECOAR/4. Structure of an application programming model
University/WUT/ECOAR/5. Application programming model
University/WUT/ECOAR/6. Execution unit
University/WUT/ECOAR/7. Pipeline execution unit
University/WUT/ECOAR/8. Multipipelined (superscalar) processors
University/WUT/ECOAR/9. Caches
University/WUT/ECOAR/11. Resource management and protection
University/WUT/ECOAR/12. Memory management
University/WUT/ECOAR/13. Exceptions
University/WUT/ECOAR/14. Input-Output

Lab lectures

University/WUT/ECOAR/L1. Introduction to assembly and hybrid programming
University/WUT/ECOAR/L2. Program creation process
University/WUT/ECOAR/L3. Assembly programming in OS environment
University/WUT/ECOAR/L4. Hybrid programming
University/WUT/ECOAR/L5. Assembly programming techniques
University/WUT/ECOAR/L7. x86 architecture and programming

University/WUT/ECOAR/x86 Programming
University/WUT/ECOAR/x86 Hybrid Programming
University/WUT/ECOAR/x86 Instruction Set
University/WUT/ECOAR/ARM Architecture

University/WUT/ECOAR/Assembly Cheatsheet - RISC V
University/WUT/ECOAR/Labs
University/WUT/ECOAR/Practical exercises
University/WUT/ECOAR/Final prep
University/WUT/ECOAR/Sample questions
University/WUT/ECOAR/RISC-V Project

Test 2

Execution Units
Pipeline
Delays
Hazards
Caches
Cache-Efficiency Models
Hit/Miss Ratio
System Parts (System Protections)
Processor Priority
Peripheral Protection
Exception Processing
Examples of Exceptions
Serving of Peripherals
Mass storage Devices