Fundamentals of Logic Circuit Design

Combinatorial Logic

Logic circuits are electronic circuits processing two-valued signals. Their operations are described by logic functions (Boolean algebra).

Boolean algebra

Laws

xy=xy=xy
xy=x+y

Truth table
x y x+y
0 0 0
0 1 1
1 0 1
1 1 1
Commutative Law

xy=yx
x+y=y+x

Distributive Law

x(y+z)=(xy)+(xz)
x+(yz)=(x+y)(x+z)

Absorptive Law

AB+A=A
AB¯+A=A
A¯B+A=A+B
AB+A¯=A¯+B
A¯B+A¯=A¯
A¯B¯+A=A+B¯
AB¯+A¯=A¯+B¯
A¯B¯+A¯=A¯

Useful

x+x=x
1=x+x¯

de Morgan's Laws

x¯+y¯=xy
x¯y¯=x+y

Examples

1

A¯+D¯+(B+AD)(C+D)
=A¯+D¯+BC+BD+AD(C+D)
=A¯+D¯+[B+BC]+AD(C+D)
=A¯+B+D¯+AD(C+D)
=A¯+B+D¯+ADC+AD
=[A¯+AD]+B+D¯
=A¯+B+D+D¯
=A¯+B+1
=1

2

BC+B¯CD¯+CD
=BC+C(B¯D¯+D)
=BC+C(B¯+D)
=BC+B¯C+CD
=C+CD
=C

3

(BC¯+D)(B¯+C)D¯
=BC¯B¯D+BC¯CD¯+DB¯D¯+DCD¯
=0+0+0+0
=0

4

BC¯+D+(B¯+C)D¯
=BC¯+D+B¯D¯+CD¯
=BC¯+C+B¯D¯+D
=BC¯+C+B¯D¯+D
=B+C+B¯+D
=C+D+1
=1

Basic gates

rM drawing 2025-10-19-23.43.03.png

Typical gates have 2n inputs, so if we want to have 5 inputs, we need to use 8-input gate.
In case of the AND gate, the rest 3 inputs need to be connected to 1

Algebraic manipulation of expressions can lead to the reduction of the circuit size

NOT and OR are the most basic gates
we can create any possible circuit using only NAND gates, or NOR gates.

Useful expressions:
ab¯+c=ab¯c
(a+b)c=(a+b)+c very popular in current designs

Logic function minimalization

yr=xaxb¯xc¯xd+xaxbxc¯xdyr=xaxc¯xd¯(xb¯+xb)yr=xaxc¯xd¯

Gray's Code

The idea of Gray's code is that the consecutive states differ only by one bit, not the value of the bits

3 bit
000
001
011
010
110
111
101
100

4 bits
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

General idea of absorption law is that it works on pairs only.
But we can technically make it work on bigger sets.

Karnaugh tables

Sum of products
yr=(2,6,9,11,12,13)

rM drawing 2025-10-19-23.34.44.png|250
Top row and left column contain inputs, and middle of the table contains every possible output.

How to solve - Sum of Products

We're interested in which inputs give ur output 1
We circle 1's together (groups of 2, 4, 8...)
Those groups can be in line, in a square, or made by 'jumping' from one edge of another (think like snake game)
Then, we check which inputs change on those outputs, and we eliminate them, so we're left only with static inputs for given outputs

So for the top right 'island' - B changes, A, C and D are static.
Now, we write AND of all those inputs, so for our island it will be A¯CD¯
For most-left island - ABC¯
Bottom island - AB¯D
So the whole output function will be Y=A¯CD¯+ABC¯+AB¯D

To remember

Sometimes, we don't need all outputs that we have available (explained in the beginning of Basic gates)
In that case, we put '-' instead of a output in the Karnaugh table. This is called a DONTCARE

When solving K-maps, when we circle DONTCARE, it gets turned
into 1, if not - into 0.
Thanks to that, DONTCAREs can be used like 'blanks' in scrabble

Product of sums
Fy0={5,13,14}

rM drawing 2025-11-02-23.49.57.png|250

y=(xa¯+xb¯+xc¯+xd)(xb¯+xc+xd¯)=(5,13,14,(2))
Quine McCluskey method

Computer software way of solving boolean algebra

Static hazards

rM drawing 2025-11-03-00.01.19.png|250

y=A¯C¯+AB

rM drawing 2025-11-03-00.00.38.png|250
A static hazard it present for two neighboring 1's that aren't in the same minterms
rM drawing 2025-11-03-00.02.53.png|250
When transitioning from a state 110 into 010
rM drawing 2025-11-03-00.05.27.png
But to correctly show the steps, we need to split the diagram into stages.
rM drawing 2025-11-03-00.10.51.png|400
When switching from 110 to 010, the top AND gate gets updated at the same time as bottom NOT gates, but because the bottom signal has to travel also through an AND gates, the final OR gets a split moment signal, where the top input is already updated, but the bottom didn't catch up yet. This is called a static hazard.

Fix

To fix the hazard, we can find the edge on the K-map that creates the problem and create a minterm from the 1's. This introduces a new part of the circuit that ensured the proper functioning of the whole circuit.

K-map

rM drawing 2025-11-03-00.20.04.png|300

Updated circuit

rM drawing 2025-11-03-00.17.41.png|300